A Node Interface for Parallel Processing

PhD Thesis, 1989

Mark R. Hammes

Abstract

A multiprocessor communication scheme for large parallel systems is devised to offer total inter-connectivity which is software programmable. The system combines associative addressing with data broadcasting along a global bus to virtually eliminate communications overheads in iterative, or cyclic, applications.

An overall introduction to parallel processing machines is given in chapter 1 and leads to an extended treatment in chapter 2 of the limitations inherent in a range of communication techniques currently employed in multiprocessor systems for parallel processing. A new communication scheme can only be devised successfully after fully considering the concepts that underlie the range of target applications. Performance models are then formulated to assess the effectiveness of the new scheme compared to a conventional common memory system. Only then will the detailed specification of the design be made. The result is a MUlti Processor Interface (MUPI) to be integrated on a single semi-custom silicon device to perform all interprocessor communications for a Multi Interfaced-Node Net for Iterative Environments (MINNIE). Chapter 3 deals with this process of devising the new scheme. Implementation details of turning the design into working hardware is carried out in two stages: a 4-node prototype system using the XILINX programmable device, followed by a full 64 node system using an MCE gate array. Verification of the effectiveness of the proposed system is dealt with in chapter 5 where, based upon the extensive use of the system, a new performance model is formulated to include basic hardware parameters. Numerical examples are given to explore the performance as the speed of the bus and allocator are increased. Summing up and suggestions for future work are given in chapter 6.